5 ms·
Better HDLs would be great, like actual HLS, BlueSpec, or Handel-C, not lame gatelist generators in a botched FP language crawling on top of Java.
by FullyFunctional 4y ago
Better HDLs would be great, like actual HLS, BlueSpec, or Handel-C, not lame gatelist generators in a botched FP language crawling on top of Java.
- ColonelPhantom 4y agoBoth approaches have virtues. HLS is simpler for software programmers, but tends to rely more on 'magic' and is not a very clean abstraction of the hardware that's generated. That said, loops aside, most compiler IR is a sort of dataflow graph which could reasonably be synthesized into hardware. But most control flow does not map very well. Higher-level HDLs such as Chisel (although I have never used it) instead abstract directly over standard HDLs like Verilog or VHDL. These abstractions are simpler because they do not alter the fundamental design ideas; they just offer increased flexibility (for example VexRiscv, which is written in SpinalHDL and has most functionality in 'plugins' which extend CPU components, which is a very powerful form of metaprogramming that is not possible with Verilog). If your issue is with Scala, there's other HHDLs such as Clash (based on Haskell) or Migen and Amaranth which use Python.