3 ms·

Hmm, wasn't aware that someone found a TSO sysctl that actually does something. The rest of my opinion is based off of these three Twitter threads: https://tw

• anyfoo 4y ago
  It's not a sysctl, it gets switched on or off during context switch. So, per thread. In any case, I'm pretty sure that marcan is aware of that, and I haven't read anything from him that would point to the contrary.
• messe 4y ago
  To clarify, the sysctl is related to a 3rd-party kernel extension. That kernel extension is a convenient wrapper around the actual interface which is a per-thread flag that can be turned on and off. And not one of those threads indicates that there is no Rosetta-related instructions. The first would indicate that marcan believes that M1 chips do have TSO related instructions. The second discusses the fact that Rosetta runs on non-Apple CPUs without TSO enabled, meaning that it running on Asahi linux without Asahi linux having TSO support does not show that M1 chips always run in TSO mode; but rather that Rosetta itself has no way of detecting it, so will attempt to run regardless. The third repeats what I just said. The twitter threads provide more evidence against your points than for them.