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I'm sorry, but please cite some sources, because this contradicts everything that's been said about M1's x86 emulation that I've read so far. > Well, did you k

by messe 4y ago

I'm sorry, but please cite some sources, because this contradicts everything that's been said about M1's x86 emulation that I've read so far. > Well, did you know Apple ported Rosetta 2 to Linux? You can get it by running a Linux VM on macOS. It does not require any kernel changes to support in VMs, and if you extract the binary to run it on Asahi Linux, it works just fine too. None of the Asahi team did anything to support x86 TSO. Rosetta also works just fine in m1n1's hypervisor mode, which exists specifically to log all hardware access to detect these sorts of things. If there is a hardware toggle for TSO, it's either part of the chicken bits (and thus enabled all the time anyway) or turned on by iBoot (and thus enabled before any user code runs). Apple tells you to attach a special volume/FS to your linux VM in order for Rosetta to work. When such a volume is attached, it runs the VM in TSO mode. As simple as that. The rosetta binary itself doesn't know whether or not TSO is enabled, so its not surprising that it runs fine under Asahi. As marcan42 himself said on twitter[1], most x86 applications will run fine even without TSO enabled. You're liable to run into edge cases in heavily multithreaded code though. [1]: https://twitter.com/marcan42/status/1534054757421432833 https://twitter.com/marcan42/status/1534054757421432833 > Both of those happened purely because M1 and M2 are so hilariously wide and speculative that they trigger memory reorders no other CPU would. In other words, they're not constantly running in TSO mode? Because if they were, why would they trigger such re-orders? EDIT: I've just run a modified version of the following test program[2] (removing the references to the tso_enable sysctl which requires an extension), both native and under Rosetta. Running natively, it fails after ~3500 iterations. Under Rosetta, it completes the entire test successfully. [2] https://github.com/losfair/tsotest/ https://github.com/losfair/tsotest/

kmeisthax 4y ago
Hmm, wasn't aware that someone found a TSO sysctl that actually does something. The rest of my opinion is based off of these three Twitter threads: https://twitter.com/marcan42/status/1534053625110351872 https://twitter.com/marcan42/status/1534053625110351872 https://twitter.com/never_released/status/1534127641082593281 https://twitter.com/never_released/status/153412764108259328... https://twitter.com/marcan42/status/1534156788224098304 https://twitter.com/marcan42/status/1534156788224098304
- anyfoo 4y ago
  It's not a sysctl, it gets switched on or off during context switch. So, per thread. In any case, I'm pretty sure that marcan is aware of that, and I haven't read anything from him that would point to the contrary.
- messe 4y ago
  To clarify, the sysctl is related to a 3rd-party kernel extension. That kernel extension is a convenient wrapper around the actual interface which is a per-thread flag that can be turned on and off. And not one of those threads indicates that there is no Rosetta-related instructions. The first would indicate that marcan believes that M1 chips do have TSO related instructions. The second discusses the fact that Rosetta runs on non-Apple CPUs without TSO enabled, meaning that it running on Asahi linux without Asahi linux having TSO support does not show that M1 chips always run in TSO mode; but rather that Rosetta itself has no way of detecting it, so will attempt to run regardless. The third repeats what I just said. The twitter threads provide more evidence against your points than for them.

by messe 4y ago

kmeisthax 4y ago

Hmm, wasn't aware that someone found a TSO sysctl that actually does something. The rest of my opinion is based off of these three Twitter threads: https://twitter.com/marcan42/status/1534053625110351872 https://twitter.com/marcan42/status/1534053625110351872 https://twitter.com/never_released/status/1534127641082593281 https://twitter.com/never_released/status/153412764108259328... https://twitter.com/marcan42/status/1534156788224098304 https://twitter.com/marcan42/status/1534156788224098304

anyfoo 4y ago
It's not a sysctl, it gets switched on or off during context switch. So, per thread. In any case, I'm pretty sure that marcan is aware of that, and I haven't read anything from him that would point to the contrary.
messe 4y ago
To clarify, the sysctl is related to a 3rd-party kernel extension. That kernel extension is a convenient wrapper around the actual interface which is a per-thread flag that can be turned on and off. And not one of those threads indicates that there is no Rosetta-related instructions. The first would indicate that marcan believes that M1 chips do have TSO related instructions. The second discusses the fact that Rosetta runs on non-Apple CPUs without TSO enabled, meaning that it running on Asahi linux without Asahi linux having TSO support does not show that M1 chips always run in TSO mode; but rather that Rosetta itself has no way of detecting it, so will attempt to run regardless. The third repeats what I just said. The twitter threads provide more evidence against your points than for them.