4 ms·

Memory bandwidth can be managed by all manner of microarchitectural methods. The issue in the modern world is that doing any kind of register renaming that woul

Memory bandwidth can be managed by all manner of microarchitectural methods. The issue in the modern world is that doing any kind of register renaming that would allow issuing 4 or more instructions at a time gets convoluted very quickly. If you could crack that, the code density would be great. But in the end giving the compiler 32 or so architectural registers and adding a renaming backend with 100+ micro architectural registers is probably a good trade off and avoids gnarly logic long-paths.

Akronymus 4y ago
I could see a circular buffer implemented in the registers working. Basically keeping the top x of the stack loaded in the reigsters, and pushing/pulling values when you get close to the opposite end (pushing values to main memory if you get too full, pulling if you get too empty) Dunno if I am explaining it well. On a reread, I think I might just be stating what you did, but in different, worse, words. Definitely a VERY different hardware architecture than "normal" machines though
- actionfromafar 4y ago
  Didn't SPARC have some kind of sliding window register set?
  - ithkuil 4y ago
    And so did the Berkrley RISC design. Also notably the Intel i960 and the Itanium
  - bouvin 4y ago
    It did. I have fond memories (no doubt in part shaped by Stockholm syndrome) of writing a Pascal(ish) compiler targeting the SPARC ISA as an undergrad back in 1993 based on four? pages of ISA documentation. As I recall, handling procedure calls and returns was quite elegant.
- Joker_vD 4y ago
  AMD Am29000 family had exactly that. The problem is, you still have to be able to name registers indirectly, or you'll have to either give up on separate compilation or do link-time intra-procedural register allocation. Both of those things are, of course, feasible in small embedded environments... but not in general-purpose computing, especially if you want to bring in most of the pre-existing software in.
- anamax 4y ago
  The problem isn't just faking a stack with a fast buffer, it's figuring out where the sources are, or rather, will be, with pipelined execution, or worse yet, decoding multiple instructions at once. You also want to have multiple instructions writing a given architectural resource live at once. That's tough if top-of-stack is a buffer location.

Akronymus 4y ago

I could see a circular buffer implemented in the registers working. Basically keeping the top x of the stack loaded in the reigsters, and pushing/pulling values when you get close to the opposite end (pushing values to main memory if you get too full, pulling if you get too empty) Dunno if I am explaining it well. On a reread, I think I might just be stating what you did, but in different, worse, words. Definitely a VERY different hardware architecture than "normal" machines though

actionfromafar 4y ago
Didn't SPARC have some kind of sliding window register set?
- ithkuil 4y ago
  And so did the Berkrley RISC design. Also notably the Intel i960 and the Itanium
- bouvin 4y ago
  It did. I have fond memories (no doubt in part shaped by Stockholm syndrome) of writing a Pascal(ish) compiler targeting the SPARC ISA as an undergrad back in 1993 based on four? pages of ISA documentation. As I recall, handling procedure calls and returns was quite elegant.
Joker_vD 4y ago
AMD Am29000 family had exactly that. The problem is, you still have to be able to name registers indirectly, or you'll have to either give up on separate compilation or do link-time intra-procedural register allocation. Both of those things are, of course, feasible in small embedded environments... but not in general-purpose computing, especially if you want to bring in most of the pre-existing software in.
anamax 4y ago
The problem isn't just faking a stack with a fast buffer, it's figuring out where the sources are, or rather, will be, with pipelined execution, or worse yet, decoding multiple instructions at once. You also want to have multiple instructions writing a given architectural resource live at once. That's tough if top-of-stack is a buffer location.