What I'm seeing right now (my feeling about new silicon) is numerous simple cores with varied memory access patterns (stream processing, large scratchpad, systo

What I'm seeing right now (my feeling about new silicon) is numerous simple cores with varied memory access patterns (stream processing, large scratchpad, systolic things, message passing over crazy fabrics...) and little to no silicium dedicated to handling complex data access patterns or complex control flow. The main motivation seems to be 'easy to tape out in one go' which is great in a sense (you get new hw faster & cheaper, with far less risk). We're seeing exploration on how to break even the gpu model's upcoming limits. Sparse algebra, taskgraph/dataflow oriented prepared or JITed pipelines, and lots of work expected from the compiler and the developer. Even the tensor or rt on nvidia gpus are strange specialized beasts there, difficult to use, especially in generic ways. Seems like a decade of niche optimisation work on dozens of new architectures is coming...