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>> I’m tired of the dominance of the out-of-order processor. They are large and wasteful, the ever-popular x86 is especially poor, and they are hard to understa

>> I’m tired of the dominance of the out-of-order processor. They are large and wasteful, the ever-popular x86 is especially poor, and they are hard to understand. Their voodoo would be more appreciated if they pushed better at the limits of computation, but it’s obvious that the problems people solve have a latent inaccessible parallelism far in excess of what an out-of-order core can extract. One thing I find interesting is the recent focus on branch predictors. OoO designs like Zen and *Lake have been seeing performance improvements due to better branch prediction (and going back, things like trace cache) which strongly suggests that flow control is very important and therefore, data-parallel code is not the majority. There is no architecture that optimally fits "general purpose computing" so we have OoO, Vector instructions, Hyper Threading, Multi-core, GPUs, and TPUs. My hope is that GPU/TPU/ML will converge on something that is very good at all 3. But maybe my hope there is due to my lack of hands-on with those.

touisteur 4y ago
What I'm seeing right now (my feeling about new silicon) is numerous simple cores with varied memory access patterns (stream processing, large scratchpad, systolic things, message passing over crazy fabrics...) and little to no silicium dedicated to handling complex data access patterns or complex control flow. The main motivation seems to be 'easy to tape out in one go' which is great in a sense (you get new hw faster & cheaper, with far less risk). We're seeing exploration on how to break even the gpu model's upcoming limits. Sparse algebra, taskgraph/dataflow oriented prepared or JITed pipelines, and lots of work expected from the compiler and the developer. Even the tensor or rt on nvidia gpus are strange specialized beasts there, difficult to use, especially in generic ways. Seems like a decade of niche optimisation work on dozens of new architectures is coming...

touisteur 4y ago

What I'm seeing right now (my feeling about new silicon) is numerous simple cores with varied memory access patterns (stream processing, large scratchpad, systolic things, message passing over crazy fabrics...) and little to no silicium dedicated to handling complex data access patterns or complex control flow. The main motivation seems to be 'easy to tape out in one go' which is great in a sense (you get new hw faster & cheaper, with far less risk). We're seeing exploration on how to break even the gpu model's upcoming limits. Sparse algebra, taskgraph/dataflow oriented prepared or JITed pipelines, and lots of work expected from the compiler and the developer. Even the tensor or rt on nvidia gpus are strange specialized beasts there, difficult to use, especially in generic ways. Seems like a decade of niche optimisation work on dozens of new architectures is coming...