4 ms·
Even with cheap modern equipment it should be no problem to manipulate the bus of something as glacially slow as a 286. With common bus frequencies, you don't e
by anyfoo 4y ago
Even with cheap modern equipment it should be no problem to manipulate the bus of something as glacially slow as a 286. With common bus frequencies, you don't even need to be really careful with the PCB layout, and e.g. a Zynq (FPGA+ARM SoC) is probably total overkill already but convenient and fun.
But the unbonded pads that you mention are a far greater concern to me...
- amluto 4y agoFrom an extremely cursory read of old webpages, it sounds like the main problem is that the signal that initiates an ICE bus transaction (ICES1# & ICES0# which, by analogy to S0 and S1 are active-low and initiate bus cycles) are unbonded. I bet a good enough guess could be made from the address and data lines to feed instructions and data to the CPU in ICE mode. Distinguishing memory reads from writes could be interesting.
- rep_lodsb 4y agoIf every instruction is prefixed with F1, the only thing going through the ICE bus would be opcode fetches.