bcantrill linked to it separately in the comments: http://dtrace.org/blogs/bmc/2008/07/18/revisiting-the-intel-432/ http://dtrace.org/blogs/bmc/2008/07/18/revis

bcantrill linked to it separately in the comments: http://dtrace.org/blogs/bmc/2008/07/18/revisiting-the-intel-432/ http://dtrace.org/blogs/bmc/2008/07/18/revisiting-the-intel-... The particular parts I was recalling are: > The upshot of these decisions is that you have more code (because you have no immediates) accessing more memory (because you have no registers) that is dog-slow (because you have no data cache) that itself is not cached (because you have no instruction cache). Yee haw! Awesome.