4 ms·
Well, now you know the answer is almost nobody :). Xilinx and Altera have been promising efficient high level C++/openCL/CUDA -> FPGA compilation for decades n
by krapht 4y ago
Well, now you know the answer is almost nobody :).
Xilinx and Altera have been promising efficient high level C++/openCL/CUDA -> FPGA compilation for decades now and almost everybody I know has been burnt by it at work, so thanks for confirming my bias, I'll avoid OneAPI too for the present. Guess VHDL and Verilog and the old standard tooling will live for another 10 years.
Everything is always amazing for the first 80% but the last 20% is impossible to fix and you end up not saving any dev time at all.
- misnome 4y ago> I'll avoid OneAPI too for the present. I wouldn't write it off _completely_, for everyone. Compiler bugs notwithstanding, it seems to work reasonably well if you don't mind extremely long compiler cycles for running on the hardware. It gives you pretty reasonable emulation tooling to work out how well it runs, whether things are pipelined and, efficient if you know what you are looking at - but it doesn't seem to save you actually having to learn how the FPGAs work and model data flow. Of course, you are also beholden on drivers/adaptors being written to actually be able to use them.... which at this point is two chipsets, the newer of which has just been deprecated. Evaluating Xilinx HLS is next on my list, at least it seems to have the benefit of being around for much longer, and we have collaborators who have had success with the tooling.