You can use a simulation program. One of the professional ones that I like is ModelSim. You design your chip in VHDL or Verilog, compile it, and then make a (v

You can use a simulation program. One of the professional ones that I like is ModelSim. You design your chip in VHDL or Verilog, compile it, and then make a (virtual) testbench in ModelSim. Then you run your design in ModelSim. You can have a look at signals while it's running the simulation in simulated oscilloscopes or you can script a better view in Tcl/Tk or you can have the testbench assert stuff. The latter lets you do something like unit tests. I do that a lot. Note that simulations are lies. So it's helpful to find obvious bugs--but in the real world all the signals run IN PARALLEL, and they can grow phase differences depending on the routing (which is generated). The simulation cannot test all the combinations (but of course the compiler tries to make the gate to gate timing work on its own). Open source variants exist. I like https://github.com/nickg/nvc.git https://github.com/nickg/nvc.git . In includes a compiler (from VHDL) and simulator. You can have nvc generate waveform outputs and look at those in gtkwave. It's neat. But it's not as full-featured as ModelSim. Eventually, you can buy an FPGA development board like the Terasic DE10-Nano and download the program Quartus Prime and actually synthesize your design and load it on the board. You need a REALLY beefy computer to do the synthesis in finite time.