4 ms·
>1 involving multiple primitives and you can't attach a signal logger to the signal between them because the FPGA doesn't have a path there to use. Does the pr
by CorrectHorseBat 4y ago
>1 involving multiple primitives and you can't attach a signal logger to the signal between them because the FPGA doesn't have a path there to use.
Does the problem not arise in simulation?
- moring 4y agoI don't have simulation models for the primitives, and I can't write them due to the lack of documentation. One of the downsides of working purely with the free / open-source toolchain, I guess. edit for clarification: The lack of simulation models is due to the free toolchain. The documentation is fully available, it's just so bad that you don't even know what some of the primitives are meant to do.