3 ms·
My guess is that to get low latency you have to be interacting with a memory controller that expects low latency (like dram) I don’t know how many cycles it wou
by MobiusHorizons 4y ago
My guess is that to get low latency you have to be interacting with a memory controller that expects low latency (like dram) I don’t know how many cycles it would take as a difference, but my impression is that pcie trades throughput for latency compared to dram
- formerly_proven 4y agoIIRC permissible lane skew in PCIe is like 30 ns, which means that the latency due to deskewing alone in PCIe already approaches main memory latency.