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planning/development for progressively lower N-nm chips seems to happen extremely far in advance - here we are talking about 2-nm when 3-nm is still around the
by 2bitencryption 4y ago
planning/development for progressively lower N-nm chips seems to happen extremely far in advance - here we are talking about 2-nm when 3-nm is still around the corner.
My question is, does the development of 2-nm happen totally independently of 3-nm? Are they happening concurrently, and 3-nm just got a head start?
Do the advances made during development of 3-nm factor in to the design of 2-nm?
Or is each "N-nm" a somewhat clean slate that brings an entirely new process?
Does each fab invent its own process for N-nm? Or does the "N-nm process" for TSMC look the same as another fabs?
(replies need not say "ackshually, 2-nm is not really 2-nm". we all know this. 90% of the comments so far are about this haha)
- jbverschoor 4y agoThe whole world is running on ASMI/ASML machines and tech.. Not TSMC's
- deleted 4y ago[deleted]
- nwiswell 4y agoThis is a gross misrepresentation analogous to saying the whole world runs on Rolls-Royce's tech, not Boeing's.
- jbverschoor 4y agoMore like all the airlines fly Boeing.
- deleted 4y ago[deleted]
- terrorOf 4y ago
- nwiswell 4y agoGood questions. At the foundry level, roadmap and research is always ongoing many nodes into the future. The degree of resources provided to a node is of course proportional to how close to becoming a source of revenue it is. Typically different nodes are owned by different development organizations, but they will frequently share development insights with each other. Sometimes the "more researchy" nodes come up with something so great that adoption gets pulled in closer to the current node. Throughout this process, the foundry is in discussions with OEMs (AMAT, Lam, TEL, ASML, ASM etc), iteratively providing product requirements, and then as the manufacturing cut-in date approaches, a winning vendor/tool is selected for each layer/unit step for the node in question, and the device integration is frozen for high volume manufacturing. > Does each fab invent its own process for N-nm? Or does the "N-nm process" for TSMC look the same as another fabs? They all use the same OEMs, and device physics and scaling is the same for everybody, so typically they end up looking pretty similar. However often there is no clear "best" way to solve an integration problem, so you you end up with different solutions depending on the foundry -- and often those solutions are driven more by business considerations and existing supplier relationships than technical merit. In other cases somebody (historically, Intel) comes up with an idea so powerful (FinFET) that everyone else (TSMC) steals it.