Those names are relevant in planar processes (32 nm was last planar prosess for Intel). With FinFets, Gate-All-Around, ribbon fet etc. that makes no sense. The

Those names are relevant in planar processes (32 nm was last planar prosess for Intel). With FinFets, Gate-All-Around, ribbon fet etc. that makes no sense. The correct figure of merit is transistor density MTr/mm² (millions of transistors per squared millimeter). In reality transistor count is not actually transistor count. Transistor count = 0.6 × NAND2/area + 0.4×[Scan Flip Flops]/area