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Yeah, it's annoying, but you can see how it happened: the nomenclature was accurate from 10µm to 32nm, and became marketing rather than measurement slowly, not
by samatman 4y ago
Yeah, it's annoying, but you can see how it happened: the nomenclature was accurate from 10µm to 32nm, and became marketing rather than measurement slowly, not all at once.
The choices are rename everything in the past according to a new objective standard (impractical), make a clean break and use a new objective standard (but what?), or just let 'nm' become some rough and increasingly useless way of indicating die density, where lower is better. So that's what happened.
- not2b 4y agoUp until about 2003 or so, scaling worked near-perfectly, so geometries were essentially the same from generation to generation. This meant that one number, describing minimum feature size, told you what you needed to know. Eventually leakage current became a major issue, so fabs had to do major redesign and change the shapes of the transistors, and different foundries did this differently so that minimum feature length is no longer directly comparable. You can still compare density: how many transistors or gates in a given area.
- scrlk 4y ago> You can still compare density: how many transistors or gates in a given area. I would say that comparing density comes with its own caveats. E.g. SRAM is denser than logic, so a chip with a lot of cache could skew a density metric. I guess for a true "apples to apples comparison" of processes you'd want to implement the same design on separate nodes with a mixture of SRAM & logic. Are there any reference designs used for this?
- unethical_ban 4y agoWhy is it impractical? I know nothing about CPU architecture. Clearly we aren't measuring performance with x-nm terminology, but the manufacturing process. Can we not use transistor density per mm^2, or if 3-dimensional, by mm^3?