IIRC the "Apicula" project for yosys/nextpnr support for Gowin FPGAs is pretty good, but still lacks a few key features for many designs - most importantly, Blo

IIRC the "Apicula" project for yosys/nextpnr support for Gowin FPGAs is pretty good, but still lacks a few key features for many designs - most importantly, Block RAM, but also PLLs and I think serdes/transceivers? I have one of the "4K" versions of this board (which also has an onboard Cortex hard core) and unfortunately still have to use the Gowin EDA suite for a lot of projects. It's getting there, though!