4 ms·

You can avoid using abstractions and write it directly on the silicon, it's not really difficult, it turns into a bunch of muxes, registers and adders (as shown

You can avoid using abstractions and write it directly on the silicon, it's not really difficult, it turns into a bunch of muxes, registers and adders (as shown in the link below) and solves the problem in just 333 clock cycles, using a minimum of power https://gist.github.com/vmunoz82/49de4c63bee1768283162ec5406b3ed4 https://gist.github.com/vmunoz82/49de4c63bee1768283162ec5406... class Euler(Elaboratable): def __init__(self): self.output = Signal(19) def elaborate(self, platform): m = Module() count5 = Signal(3) c3, c5 = Signal(17), Signal(18) cond3, cond5 = (c3 < 1000) & (count5 != 0), (c5 < 1000) & (count5 < 3) m.d.sync += count5.eq(Mux(count5 == 4, 0, count5+1)) m.d.sync += [ c3.eq(c3+3), c5.eq(Mux(cond5, c5+5, c5)) ] m.d.sync += self.output.eq(self.output + Mux(cond3, c3, 0)+Mux(cond5, c5, 0)) return m

stefanpie 4y ago
Amaranth (previously nmigen) is super awesome declarative ways to build circuits. I like to think of it as a superior verilog alternative that lets you do RTL design in Python. Being able to use python constructs to dynamically build logic like in the example is super useful. You can integrate it with other things like scikit-learn, numpy, and script to build things like filters and hardware accelerators.
shawnnapora 4y ago
This is pretty neat! Is there a way to have arbitrary input for the number of cycles and actually emit the answer? It looks like the answer is being read in software from a register, if I understand the .vcd output correctly.
- victor82 4y ago
  Well, that code is module without any context (ie: connected to nothig), it just have 2 inputs (clk and rst), and an "output" with the current sum, after it reach the desired value it keep stuck there (until reset). So as the simulation code shows, it just tick the clock (with the "yield" statement) and read the "output" register and print it. Of course you could connect this "Project Euler 1 accelerator" to a CPU, a SoC or whatever, or just connect LEDs directly to "output"
rowanG077 4y ago
I'm not sure if I think this superiour to Verilog. It's way less readable but it does have the advantage of having insane metaprogramming ability. It's basically a circuit templating language. Really sucks the syntax is so unreadable.

stefanpie 4y ago

Amaranth (previously nmigen) is super awesome declarative ways to build circuits. I like to think of it as a superior verilog alternative that lets you do RTL design in Python. Being able to use python constructs to dynamically build logic like in the example is super useful. You can integrate it with other things like scikit-learn, numpy, and script to build things like filters and hardware accelerators.

shawnnapora 4y ago

This is pretty neat! Is there a way to have arbitrary input for the number of cycles and actually emit the answer? It looks like the answer is being read in software from a register, if I understand the .vcd output correctly.

victor82 4y ago
Well, that code is module without any context (ie: connected to nothig), it just have 2 inputs (clk and rst), and an "output" with the current sum, after it reach the desired value it keep stuck there (until reset). So as the simulation code shows, it just tick the clock (with the "yield" statement) and read the "output" register and print it. Of course you could connect this "Project Euler 1 accelerator" to a CPU, a SoC or whatever, or just connect LEDs directly to "output"

rowanG077 4y ago

I'm not sure if I think this superiour to Verilog. It's way less readable but it does have the advantage of having insane metaprogramming ability. It's basically a circuit templating language. Really sucks the syntax is so unreadable.