I noticed that K8's the 3-wide pipeline has 3 AGUs alongside the ALUs, which led me to wonder how modern RISC architectures handle address calculations. Do they

I noticed that K8's the 3-wide pipeline has 3 AGUs alongside the ALUs, which led me to wonder how modern RISC architectures handle address calculations. Do they still have separate AGU circuitry? [edit] After some furious Googling it looks like AGUs are still a thing in RISC architectures such as: https://en.wikichip.org/wiki/arm_holdings/microarchitectures/cortex-a77 https://en.wikichip.org/wiki/arm_holdings/microarchitectures... and https://en.wikichip.org/wiki/sifive/microarchitectures/7_series https://en.wikichip.org/wiki/sifive/microarchitectures/7_ser...