4 ms·

That outcome would be expected from either decreasing cell size, or increasing bits/cell (what used to be commonly called SLC/MLC/TLC/QLC). I don't see TFA men

That outcome would be expected from either decreasing cell size, or increasing bits/cell (what used to be commonly called SLC/MLC/TLC/QLC). I don't see TFA mentioning either directly, but there are some hints that one of the two (or both) did happen: Number of layers increased from 176 to 232 (that explains 32% increase) but bits/chip area has doubled (total density increased by 100%). Where does the rest of this increase coming from, you reckon?

HeyItsMatt 4y ago
From a much better Anandtech article: 32% increase in layers, 40% increase in die area. https://www.anandtech.com/show/17509/microns-232-layer-nand-now-shipping https://www.anandtech.com/show/17509/microns-232-layer-nand-... A bunch of the cost is test and packaging which is constant so there will be a small cost per bit reduction. But the new chip will cost significantly more to manufacture than a 512Gbit device. No free lunch.