3 ms·
A bit of a nitpick - LiteX still mostly needs Vivado installed for now for 7 series FPGAs. There's a project that's very far along in reverse engineering the Xi
by Teknoman117 4y ago
A bit of a nitpick - LiteX still mostly needs Vivado installed for now for 7 series FPGAs. There's a project that's very far along in reverse engineering the Xilinx bitstream (https://github.com/f4pga/prjxray https://github.com/f4pga/prjxray), but it's still missing many features (PCIe, SERDES, hardware multipliers, etc.). You can run on the open source toolchain but you lose so many of the reasons to actually use a Xilinx FPGA.
The only fully supported reverse engineered FPGAs at the moment are the Lattice ECP5(-5G), iCE40, and QuickLogic EOS families.
https://f4pga.readthedocs.io/en/latest/status.html https://f4pga.readthedocs.io/en/latest/status.html
- mithro 4y agoWhen did you last check? The Yosys+VPR toolchain currently supports a full Linux capable SoC with Ethernet and DDR memory on the Arty A35T (which has a Xilinx Artix 7 part), see the example at https://f4pga-examples.readthedocs.io/en/latest/building-examples.html#linux-litex-demo https://f4pga-examples.readthedocs.io/en/latest/building-exa...
- Teknoman117 4y agoA few months ago. Looks like DSP (hardware multiply-accumulate units) is partially supported now if VexRiscv is synthesizing, but there's still some open issues on their tracker about whether they understand them fully or not.
- mithro 4y agoI afraid I don't recall the status of DSP blocks in the open source toolchains for Xilinx hardware. Even if the basics are supported I'm sure there are plenty of DSP features that are not. Many configurations of VexRISCV work fine without using the DSP blocks (and has been working for 2+ years), so not sure that is relevant.