3 ms·Using Common Lisp to generate VHDL for ultra-lowlatency FPGAs4 points by medo-bear 4y agomedo-bear 4y agoalso see https://github.com/mbattyani/sub-25-ns-nasdaq-itch-fpga-parser https://github.com/mbattyani/sub-25-ns-nasdaq-itch-fpga-pars...