The thing with high-performance x86 is that it is not really an microcoded design. The CPU is RISC-like OoO thing that can execute some pretty substantial subse

The thing with high-performance x86 is that it is not really an microcoded design. The CPU is RISC-like OoO thing that can execute some pretty substantial subset of x86 ISA after some simple conversion (ie. to some fixed-width format). Thus it makes sense for such design to not have separate microcode sequencer but run the "microcode" that emulates instructions that are not directly supported through the same execution engine (with the low-level "micro" ISA having extensions to manipulate the CPU state that is not directly modifiable by user code, like filling TLBs and changing shadow descriptors).