> They should not be over subscribed as they have to context switch by storing / loading registers and the cache coherence protocols scale badly with more threa

> They should not be over subscribed as they have to context switch by storing / loading registers and the cache coherence protocols scale badly with more threads. CPUs can be oversubscribed if so designed. POWER9 had SMT4 and SMT8, (4-threads per core and 8-threads per core, respectively). SMT8 is basically GPU-level throughput / threading. SMT4 is probably a better medium between x86 (2-threads per core) and the craziness that is GPUs. > - Register renaming > - Out of order execution These are one and the same. Tomasulo's Algorithm is the key thing to understand here: https://en.wikipedia.org/wiki/Tomasulo_algorithm https://en.wikipedia.org/wiki/Tomasulo_algorithm ------- I'd describe modern CPUs to be pipelined (break up instructions to help parallelize fetch/decode/execution), superscalar (multiple execution pipelines in parallel), out-of-order (renaming / retirement units with Tomasulo's algorithm), branch predicted, speculative processors with virtual memory and MESI-like algorithms to enable cache-coherence / multicore. ------- I basically agree with your post. Just clarifying a few points. My mental model of CPUs / GPUs seems to match yours.