4 ms·
As brucehoult says on Github, that is the response: "There are many places in the design of RISC-V intended to make simple implementations simple, and high per
by panick21_ 4y ago
As brucehoult says on Github, that is the response:
"There are many places in the design of RISC-V intended to make simple implementations simple, and high performance implementations possible, at possibly a little extra complexity in the already-complex implementations that can best afford it."
Seems to me if we can make high speed x86 this one overloaded register in RISC-V is not gone make or break high speed implementation in terms of complexity.
- avianes 4y agoYes, the issue raised definitely not prevents a high-performance implementation. But it's still interesting to ask ourselves if this is not an unnecessary cost? The concern I have here is that to deal with this question you need very good microarchitecture knowledge about vector-unit, and the author doesn't seem to have them, but he reaches a confident conclusion. How does one reach a conclusion with so much confidence on a technical subject that one does not know?
- klelatti 4y agoAre you saying that only people with very good micro architecture knowledge are allowed to ask questions about the RISC-V ISA? Whilst the presentation of this as a ‘problem’ is debatable as may be some of the reasoning it doesn’t seem to me that it’s an unreasonable question to ask.
- panick21_ 4y agoI just think he really thought more about how performance then super low performance implementation. Its a good blog-post and its a point worth talking about.