3 ms·
Correct, plus big-endian, plus any emulation for opcodes not supported by the host CPU (like paired singles, or mcrxr on G5 and up), plus any cacheline size imp
by classichasclass 4y ago
Correct, plus big-endian, plus any emulation for opcodes not supported by the host CPU (like paired singles, or mcrxr on G5 and up), plus any cacheline size impedance mismatches. It should be possible to run such code in the standard PowerPC problem state but it wouldn't be trivial.