3 ms·

I have a question (I know nothing about the domain): In the article they say that the die should have 450 mils length at most. This is 11.43mm (in SI units) s

I have a question (I know nothing about the domain): In the article they say that the die should have 450 mils length at most. This is 11.43mm (in SI units) so it's a surface of 130.6449mm2 For one million transistors, this gives an area of 0.0001306449mm2 So if it was a square it would have an edge of 0.01143mm or 11.43 μm. Wikipedia says that the size of a I860 transistor at the time was from 1 to 0.8μm. Indeed the connections between transistors take much more area than the transistor itself, and power connections are much larger but the discrepancy seems still large between 1μm and 11.43 μm. Please enlighten me!

adrian_b 4y ago
"1 to 0.8μm" was not the size of a transistor, but the width of a line drawn on the die, presumably the half-pitch of the polysilicon patterns that made the gate of the MOS transistors. To draw a MOS transistor, you have to draw a source, a drain and a gate, each having a width of "1 to 0.8μm", and you must have spaces between them, about as large as their width. In most transistors, you cannot use a source, a drain and a gate of minimum width, because you need contact windows, i.e. holes through the insulating layers, to connect the inputs, outputs and power supplies of a gate. Where a contact window is placed, which is a square with a "1 to 0.8μm" side, the source/drain/gate traces must be wider, to ensure that the hole remains under or over them even when successive masks are slightly misaligned. If you draw a MOS transistor of minimum size, taking into account all the design rules, its area might be 10 to 30 times larger than the area of a square of minimum size. A large part of the transistors in a CPU are larger than the minimum size, to ensure a high enough speed for them. In old CMOS processes, like for 80860, the PMOS transistors were at least twice wider than the NMOS transistors, to decrease the PMOS "on" resistance to values similar to that of the NMOS transistors. Moreover, in a CPU, especially in old CPUs like 80860, i.e. at a time when they used much fewer metal layers than in modern chips, large areas might have contained no transistors, because they were covered by internal buses, i.e. they were used for routing many metal interconnections, leaving no place for transistors. So there are a lot of reasons why the average die area per transistor, especially in so old CPUs, must be much larger than the area of a square of minimum size. Therefore the values computed by you seem very reasonable.
- JPLeRouzic 4y ago
  Many thanks for the detailed explanation!

adrian_b 4y ago

"1 to 0.8μm" was not the size of a transistor, but the width of a line drawn on the die, presumably the half-pitch of the polysilicon patterns that made the gate of the MOS transistors. To draw a MOS transistor, you have to draw a source, a drain and a gate, each having a width of "1 to 0.8μm", and you must have spaces between them, about as large as their width. In most transistors, you cannot use a source, a drain and a gate of minimum width, because you need contact windows, i.e. holes through the insulating layers, to connect the inputs, outputs and power supplies of a gate. Where a contact window is placed, which is a square with a "1 to 0.8μm" side, the source/drain/gate traces must be wider, to ensure that the hole remains under or over them even when successive masks are slightly misaligned. If you draw a MOS transistor of minimum size, taking into account all the design rules, its area might be 10 to 30 times larger than the area of a square of minimum size. A large part of the transistors in a CPU are larger than the minimum size, to ensure a high enough speed for them. In old CMOS processes, like for 80860, the PMOS transistors were at least twice wider than the NMOS transistors, to decrease the PMOS "on" resistance to values similar to that of the NMOS transistors. Moreover, in a CPU, especially in old CPUs like 80860, i.e. at a time when they used much fewer metal layers than in modern chips, large areas might have contained no transistors, because they were covered by internal buses, i.e. they were used for routing many metal interconnections, leaving no place for transistors. So there are a lot of reasons why the average die area per transistor, especially in so old CPUs, must be much larger than the area of a square of minimum size. Therefore the values computed by you seem very reasonable.

JPLeRouzic 4y ago
Many thanks for the detailed explanation!