3 ms·

IIRC, you’re a bit wrong with the numbers. The decoder is now a fourth the size it used to be, and they’re now using 5 (up from 4).

• hajile 4y ago
  It's more nuanced than that though 75% smaller is a fourth the size (I guess depending on where you're looking from). A710 had a uop cache. A710 had 4 decoders but it was like Intel's decoders where one (I assume one, but less than all of them) decoder could decode anything and the others could decode common instructions, but would block and send complex decodes to the complex one. A715 now has not just 5 decoders, but every one of them can decode anything reducing pipeline complexity and increasing theoretical throughput (depending on how often those complex instructions would be used). A710 did instruction fusion in the uop cache, but A715 now does it in the L1 cache during fetch which increases effective instruction throughput by occasionally turning 2+ instructions into one. Finally, A710 used a uop cache. The decoders would fill the uop cache at a rate of 4 instructions per cycle (less if one of those complex decodes happened). Once the uop cache would fill, it would provide 5 instructions per cycle to the rest of the frontend. If A710 could prefetch and keep the uop cache full and there were always enough loops to reuse some parts while others were refilling, then you could keep the full 5 instruction theoretical output. A715 gets rid of all these exceptions making it more consistent. In truth, the final difference is definitely less than 20% in the real world, but even a 0% increase in throughput while getting rid of 75% of your transistors would still be a massive win.