Actually, my school has a very strict deadline and I missed it so didn't get the PhD. But there is that text and the slides of my presentation: https://prezi.c

Actually, my school has a very strict deadline and I missed it so didn't get the PhD. But there is that text and the slides of my presentation: https://prezi.com/yhw-a3i0rnri/adaptive-compilation-for-an-object-oriented-and-reconfigurab/ https://prezi.com/yhw-a3i0rnri/adaptive-compilation-for-an-o... The focus for SiliconSqueak 3 was to have a small die area for the version without the ALU Matrix coprocessor. The inclusion of a total of 20KB of caches does bump up the transistor count by 20*1024*8*6 = 983,040 transistors all by itself though these tend to be far more dense than logic transistors. The rest of the processor is reasonably small. The stack cache is organized as 32 word blocks that are aligned in memory on 32 word boundaries. At any instant pseudo registers t0 to t31 are covered by two blocks, named low and high. Adding the register number to the bottom 5 bits of the frame pointer gives you a five bit result plus carry. The carry selects between the low and high blocks while the five bit result is the word within that block. When the frame pointer moves out of the low block, new low and high blocks are selected by following a linked list. This allows stack blocks from multiple threads to live side by side in the cache.