I started working in 1997 doing digital physical design. I had never heard the term "silicon compiler" before so I looked it up. https://en.wikipedia.org/wiki

I started working in 1997 doing digital physical design. I had never heard the term "silicon compiler" before so I looked it up. https://en.wikipedia.org/wiki/Silicon_compiler https://en.wikipedia.org/wiki/Silicon_compiler Silicon compilation takes place in three major steps: Convert a hardware-description language such as Verilog or VHDL into logic (typically in the form of a "netlist"). Place equivalent logic gates on the IC. Silicon compilers typically use standard-cell libraries so that they do not have to worry about the actual integrated-circuit layout and can focus on the placement. Routing the standard cells together to form the desired logic. So this is basically what I do everyday but we just call it logic synthesis (Synopsys Design Compiler / Cadence Genus) and Place and Route in Cadence Innovus or Synopsys IC Compiler. We use Mentor Calibre for LVS/DRC. I've worked in serdes teams where there is a lot of custom analog design with manually sized transistors and custom layout in Virtuoso. I'm working on chips in 5nm that are over 20x20mm so it would be impossible to do those without all the automation and it is still tons of manual work. Some of my older coworkers told me about doing layout on transparencies and colored pencils in the early 1980's.