I built a RISC-V emulator in python focused on extensibility and debugability for this exact purpose. It should be dead simple to use with plain RISC-V Assembly

I built a RISC-V emulator in python focused on extensibility and debugability for this exact purpose. It should be dead simple to use with plain RISC-V Assembly files. It has a userspace-only mode and a minimal privileged mode: https://github.com/AntonLydike/riscemu https://github.com/AntonLydike/riscemu Adding new instructions is as simple as adding a method to a class, as long as you are reading straight assembly files. If you want to parse ELF-files, you also have to add the opcodes for your command to the decoder (which is currently not very well documented). If you'd like to do that, feel free to open an issue and I'll work you through it. I also built a minimal kernel, which works on the emulator, but it doesn't support IO and is very rough around the edges in general.