It's been posted elsewhere, diverging from the ARM Architecture Reference Manual in ways that other chips have not. New instructions in spaces like ML, decompr

It's been posted elsewhere, diverging from the ARM Architecture Reference Manual in ways that other chips have not. New instructions in spaces like ML, decompression, new privilege modes, features that are fixed on that are specficed to be optional at runtime, etc. Particularly the new instructions are damning as ARM has said they are specifically disallowing custom instructions this go around in order to combat architecture fragmentation.