I'm not a wizard in the dark arts of electricity and semiconductors, but my guess is that PCIe is optimizing for bandwidth, whereas RAM is optimizing for latenc

I'm not a wizard in the dark arts of electricity and semiconductors, but my guess is that PCIe is optimizing for bandwidth, whereas RAM is optimizing for latency. Obviously, these goals often coincide, and demands on hardware will occasionally shift one priority over the other (a good example being DDR5, higher latency, but higher bandwidth). That's really the nature of comparing two levels of cache though. Going from L2 to L3, you sacrifice latency for capacity. Same thing going from L3 to L4 (RAM), and L4 to L5 (Disk). The gaps between levels may shrink over time, but we have distinct levels as a form of cost minimization. If we could cheaply stick a terabyte of L1 cache onto a consumer grade CPU, we probably would.