3 ms·

I don't think that is big of an issue. I have designed a memory controller and since the SDRAM protocol is really unambiguous which party owns the dqs lanes at

• tails4e 4y ago
  The main issue is not who owned it, but the fact a pll (or similar) was needed to create a local clock locked to dqs, but dqs from the sender would dissappear for an unknown number of cycles depending on the rx vs TX schedule. So that local pll could drift and would need to be re locked once dqs from the sender was presented again