3 ms·
The DRAM signaling is very strange, I worked briefly on a hardware DDR controller and the timing reference was over pins called dqs. These pins sent a signal to
by tails4e 4y ago
The DRAM signaling is very strange, I worked briefly on a hardware DDR controller and the timing reference was over pins called dqs. These pins sent a signal to represent the bit transition so they could be safely captured by the receiver. All good, except the pins were bidirectional so when transmitting you sent a reference on the same pins, so lost the reference from the other side. The issue then was when you just switch from trasmitting to receiving, you have to quickly re-lock to the sending reference, which is a pain in the ass, and really complicates things. DDR phys could be simplified if dqs was unique per TX and RX directions, but nope, penny pinching on the signal count.
- rowanG077 4y agoI don't think that is big of an issue. I have designed a memory controller and since the SDRAM protocol is really unambiguous which party owns the dqs lanes at what point I never had a problem with this. I'm curious what problems you encountered.
- tails4e 4y agoThe main issue is not who owned it, but the fact a pll (or similar) was needed to create a local clock locked to dqs, but dqs from the sender would dissappear for an unknown number of cycles depending on the rx vs TX schedule. So that local pll could drift and would need to be re locked once dqs from the sender was presented again