14 ms·

The other answers miss the point. A flip flop can be calibrated to the difference potentials of thr input. You have zero and one as a result, no processing req

• rtpg 4y ago
  Am I incorrect in thinking that you can smartly place some resistors to turn your, say, 4 level voltage difference into two inputs with some resistors? It's been a long time since I took electronics but surely that's not a complex problem requiring "complex ADC" right? Though I could imagine at one point you're just looking at larger buses and having to deal with those consequences
  • magicalhippo 4y ago
    Unless I misunderstood you, what you're describing is essentially a flash ADC[1]. It's very fast, and not that complex for a low number of bits. But it scales poorly to higher bit depths. I wouldn't be surprised if that's what they'll be using, though I'm not an expert either so might be better options out there. [1]: https://en.wikipedia.org/wiki/Flash_ADC https://en.wikipedia.org/wiki/Flash_ADC
    • davrosthedalek 4y ago
      Needs comparators though, not only resistors. It's not easy to make them super fast.
      • magicalhippo 4y ago
        I don't know enough of chip design to say more, I just know it's been done[1]. I know interleaving is another approach[2] for reaching high sample rates, though it introduces latency. What other approaches are there for low-precision multi-Gs/s ADCs? [1]: https://www.analog.com/media/en/technical-documentation/data-sheets/hmcad5831.pdf https://www.analog.com/media/en/technical-documentation/data... [2]: https://www.analog.com/en/technical-articles/a-12-b-10-gss-interleaved-pipeline-adc-in-28-nm-cmos-tech.html https://www.analog.com/en/technical-articles/a-12-b-10-gss-i...
  • usrn 4y ago
    ADCs are slow. With four levels they're probably using comparators.