3 ms·

He already said it. Noise. With 2 levels you have low and high. I have no idea if PCIe is 1.8V but let’s be really gracious here and pretend it’s 5V. Ok; so a

He already said it. Noise. With 2 levels you have low and high. I have no idea if PCIe is 1.8V but let’s be really gracious here and pretend it’s 5V. Ok; so at 5V and 4 levels you have Sig Al’s between 0V, 1.25V, 2.50V, and 3.75V. And are encoding 2 bits per clock. At 64 levels you have a signal every 0.078125V. It’s going to be really hard to capture that signal at a moment in time and at these speeds be certain if it’s definitely A or B. At some point you get into modems (modulation, demodulation) but the add much more cost, latency, and complexity. So before getting into radio and analog tech, here is a simple way to double the bandwidth for little cost. A driver only needs 0,1,2,3 levels and a receiver can make fairly confident guesses quickly. I’m pretty sure PCIe isn’t 5V. Probably more like 1.8V, so already starting with a much smaller range.

bunnie 4y ago
Riding on the coat-tails of the noise problem is power. PAM-4 is an easy win because 2-level signalling is "over-margined" (which is why you don't need error correction with 2 levels, but you start to rely on it more and more as the # of levels goes up). The "easiest" way to get around noise problems is to put more signal in, but power consumption increases with the square of voltage -- so it's extremely costly to overcome noise with more signal. However, noise is a fundamental limit; there's a set of tricks you can maybe do to improve it but for example, kT/q (thermal voltage of noise at roughly room temp) is about 25mV and that plays a role in a lot of device physics. Thus most signals engineers would steer away from higher-order PAM and go to QAM, where they use phase to encode one dimension of data, and voltage to encode the other. This gets you out of a one-dimensional line of voltages and into a two-dimensional matrix of voltage vs. time to represent information. This helps fight against that square-law term for power, but it comes at the expense of more precise timing sources. Time also has noise mechanisms, that are typically only overcome at the expense of -- you guessed it -- power. At the end of the day, probably the most fundamental limit all computation will run into is power -- both how much you can afford to put in, and more importantly, the limit of what you can pull out reliably and efficiently. I'd be curious to see the plot of PCI-express energy-per-bit over its generations...I suspect it improves over time, but not improving as fast as bandwidth is going up, which means in net each link should run hotter.
voxadam 4y ago
> I’m pretty sure PCIe isn’t 5V. Probably more like 1.8V, so already starting with a much smaller range. I'm fairly sure the most modern PCIe standards are all the way down to 1.2V. Prior to 1.2V it was 1.5V, 1.8V, 2.5V, and back in the days of the original spec it was 3.3V. I can't remember exactly what versions speced what voltages.
- Kirby64 4y ago
  Modern PCIe uses a complicated transceiver design that does pre-emphasis/de-emphasis on the signal. The actual signal swing is differential, and on the order of +/-200mV (with a relatively low voltage common mode, on the order of 300mV) after all the attenuation. What the actual digital IO voltage that the chip that does PCIe driver is driven from is almost unrelated.
megous 4y ago
More like +-350mV

bunnie 4y ago

Riding on the coat-tails of the noise problem is power. PAM-4 is an easy win because 2-level signalling is "over-margined" (which is why you don't need error correction with 2 levels, but you start to rely on it more and more as the # of levels goes up). The "easiest" way to get around noise problems is to put more signal in, but power consumption increases with the square of voltage -- so it's extremely costly to overcome noise with more signal. However, noise is a fundamental limit; there's a set of tricks you can maybe do to improve it but for example, kT/q (thermal voltage of noise at roughly room temp) is about 25mV and that plays a role in a lot of device physics. Thus most signals engineers would steer away from higher-order PAM and go to QAM, where they use phase to encode one dimension of data, and voltage to encode the other. This gets you out of a one-dimensional line of voltages and into a two-dimensional matrix of voltage vs. time to represent information. This helps fight against that square-law term for power, but it comes at the expense of more precise timing sources. Time also has noise mechanisms, that are typically only overcome at the expense of -- you guessed it -- power. At the end of the day, probably the most fundamental limit all computation will run into is power -- both how much you can afford to put in, and more importantly, the limit of what you can pull out reliably and efficiently. I'd be curious to see the plot of PCI-express energy-per-bit over its generations...I suspect it improves over time, but not improving as fast as bandwidth is going up, which means in net each link should run hotter.

voxadam 4y ago

> I’m pretty sure PCIe isn’t 5V. Probably more like 1.8V, so already starting with a much smaller range. I'm fairly sure the most modern PCIe standards are all the way down to 1.2V. Prior to 1.2V it was 1.5V, 1.8V, 2.5V, and back in the days of the original spec it was 3.3V. I can't remember exactly what versions speced what voltages.

Kirby64 4y ago
Modern PCIe uses a complicated transceiver design that does pre-emphasis/de-emphasis on the signal. The actual signal swing is differential, and on the order of +/-200mV (with a relatively low voltage common mode, on the order of 300mV) after all the attenuation. What the actual digital IO voltage that the chip that does PCIe driver is driven from is almost unrelated.

megous 4y ago

More like +-350mV