3 ms·

I don't believe it. A quick search seems to indicate that the IBM PC 5150 triggered memory refresh via timer hooked up to an interrupt which would trigger the r

by Cerium 4y ago

I don't believe it. A quick search seems to indicate that the IBM PC 5150 triggered memory refresh via timer hooked up to an interrupt which would trigger the refresh hardware without cpu support.

tibbydudeza 4y ago
There were computers before the IBM PC you know :).
- Cerium 4y ago
  Do you have one in mind? I'd love to read some.
  - tasty_freeze 4y ago
    The Apple II used DRAM (4KB was the minimum initially). There was no refresh logic. The CPU was slow (just a bit more than 1 MHz), and DRAM could perform two complete RAS cycles in that time. That allowed the design to perform one memory operation per CPU cycle and do one DRAM read for video display per cycle. The mapping of logical addresses to DRAM rows was designed such that during normal video display every row was touched frequently enough that it met refresh requirements. Z80 CPUs had DRAM refresh logic built in. The first two clock cycles it would read the primary opcode byte, and the next two clock cycles it would do a refresh of the next row and then increment the row counter ("R"). That worked well because the minimum instruction took four clock cycles to complete. The timing was a bit surprising though -- it would seem to take four cycles to fetch the first byte of an instruction but only three clock cycles for each subsequent memory transaction. Unfortunately, the R counter was only 7b wide, which was fine for 16Kbit DRAMs, but became a problem for 64Kbit DRAMs which needed to refresh 256 rows, not just 128. Some Z80 based designs would decode the refresh cycles and either mux in their own 8b count value, or they ignored the Z80 and just stall the Z80 every so often to perform a refresh cycle.
    - lanstin 4y ago
      I had an Ohio Scientific Challenger 1p (not totally sure on the numbers and letters) which I am pretty sure had 8K static RAM for main memory and a 1K video RAM for character addressable graphics. Microsoft BASIC in ROM and a tiny hex monitor for doing assembly. https://www.pcjs.org/machines/osi/c1p/ https://www.pcjs.org/machines/osi/c1p/
  - fsckboy 4y ago
    look up CP/M systems and or S-100 bus systems (they're generally the same machines)

by Cerium 4y ago

I don't believe it. A quick search seems to indicate that the IBM PC 5150 triggered memory refresh via timer hooked up to an interrupt which would trigger the refresh hardware without cpu support.

tibbydudeza 4y ago

There were computers before the IBM PC you know :).

Cerium 4y ago
Do you have one in mind? I'd love to read some.
- tasty_freeze 4y ago
  The Apple II used DRAM (4KB was the minimum initially). There was no refresh logic. The CPU was slow (just a bit more than 1 MHz), and DRAM could perform two complete RAS cycles in that time. That allowed the design to perform one memory operation per CPU cycle and do one DRAM read for video display per cycle. The mapping of logical addresses to DRAM rows was designed such that during normal video display every row was touched frequently enough that it met refresh requirements. Z80 CPUs had DRAM refresh logic built in. The first two clock cycles it would read the primary opcode byte, and the next two clock cycles it would do a refresh of the next row and then increment the row counter ("R"). That worked well because the minimum instruction took four clock cycles to complete. The timing was a bit surprising though -- it would seem to take four cycles to fetch the first byte of an instruction but only three clock cycles for each subsequent memory transaction. Unfortunately, the R counter was only 7b wide, which was fine for 16Kbit DRAMs, but became a problem for 64Kbit DRAMs which needed to refresh 256 rows, not just 128. Some Z80 based designs would decode the refresh cycles and either mux in their own 8b count value, or they ignored the Z80 and just stall the Z80 every so often to perform a refresh cycle.
  - lanstin 4y ago
    I had an Ohio Scientific Challenger 1p (not totally sure on the numbers and letters) which I am pretty sure had 8K static RAM for main memory and a 1K video RAM for character addressable graphics. Microsoft BASIC in ROM and a tiny hex monitor for doing assembly. https://www.pcjs.org/machines/osi/c1p/ https://www.pcjs.org/machines/osi/c1p/
- fsckboy 4y ago
  look up CP/M systems and or S-100 bus systems (they're generally the same machines)