4 ms·
The 6502 can only address 2^16 bytes of memory, so you could just build that as a modern L1 cache. Heck, you might even be able to put 2^16 registers on the di
by vikingerik 4y ago
The 6502 can only address 2^16 bytes of memory, so you could just build that as a modern L1 cache. Heck, you might even be able to put 2^16 registers on the die these days. (You could say this falls under your "exotic ram" clause.)
You could also do pipelining and parallel/out-of-order execution like modern processors, if you weren't worried about retaining cycle-for-cycle compatibility. You could even build it with a wider bus, so that you could read all of a 2/3/4 byte instruction in one cycle. Although at that point it's really semantics as whether you call it a 6502 or a new processor with binary compatibility.
- shadowofneptune 4y agoThe zero page is small enough to fit into a single vector register nowadays. Since the zero page is used like a register file, that alone could be a big advantage.
- toast0 4y ago> you could just build that as a modern L1 cache. I think this could work, although if that means the ram is on die, setting up the memory map is much more complex (although maybe you just have a chip select pin for the on-die ram, and have your address decoder circuitry select it when appropriate for your system) > You could also do pipelining and parallel/out-of-order execution like modern processors I don't think that fits the prompt of same fundamental design though.
- flohofwoe 4y ago> setting up the memory map is much more complex This is where the Z80 would come in handy with its separate 16-bit IO address space (accessed through special IO instructions and on the hardware level an IORQ output pin). The Z80 can also easily handle slow memory and IO devices through its WAIT input pin (but of course this just causes the CPU to slow down to the speed of the memory or IO device).