3 ms·
Enough of a pain that SiFive cores take a whole extra cycle for LB/LH (and LW on 64 bit) from L1 cache compared to loading a full register e.g. 3 vs 2.
by brucehoult 4y ago
Enough of a pain that SiFive cores take a whole extra cycle for LB/LH (and LW on 64 bit) from L1 cache compared to loading a full register e.g. 3 vs 2.