The official press release for 6.0 states: > Almost like clockwork, PCI-SIG has doubled PCIe specification bandwidth every three years to meet the challenges o

The official press release for 6.0 states: > Almost like clockwork, PCI-SIG has doubled PCIe specification bandwidth every three years to meet the challenges of emerging applications and markets. This is not a perfect cadence. 5.0 was only 2 years. 4.0 was 7 years. But it's not a bad back of napkin figure. As for buses getting faster, it's a mix of market demand and improved technology. Market demand is that we have SSDs, network cards, graphic cards, and soon expandable memory (CXL & perhaps others) that need the throughput, where-as for a while it was kind of exotic just having a 100Gbit ethernet port (12x ports worth at 3.0 speeds) or two in a system. Similarly, getting to 4GBps capable SSDs took a while, as we learned to stack layer after layer of flash & build better controllers. The demand wasn't there. But we've really scaled up a lot lately. And yeah the tech has improved. We've gotten a lot better at building transceivers. PCIe 5.0 is 32GT/s, which is "only" 60% faster than DisplayPort 2.0 which does 20GT/s over a much lower quality much more challenging channel. For PCIe 6.0, instead of jacking up the speed, we use PAM4 to effectively send two bits at a time (32Gbaud * 2bit). PCIe 7.0 will be another speed bump (64Gbaud * 2bit), and isn't going to be super easy, but we'll have very carefully specified channels, be using newer lower-power higher-efficiency designs... it'll be hard but we need that high target to shoot for, to have growing room. In some ways, this is all just downstream of what datacenter ethernet does & needs. 400Gbe is here & often uses 8 lane connections (QSFP-DD), so 50GT/s on each lane from the switch to the transciever and/or cable (which by the way look awesome [1]). But we're already well underway doubling that, to 800Gbe and terabit ethernets, so we're already making quite a lot of silicon that does 64GT/s+. Simply leveraging what we know about signalling in other places, & bringing that wisdom & experience to PCIe, makes sense. [1] https://www.fs.com/products/82459.html?attribute=3424&id=175976 https://www.fs.com/products/82459.html?attribute=3424&id=175...