4 ms·

Is it me or does it seem like they are releasing a new version every year? I just upgraded to PCIe 4.0 last year, and I was on 3.0 for what I think was 8 or 9 y

Is it me or does it seem like they are releasing a new version every year? I just upgraded to PCIe 4.0 last year, and I was on 3.0 for what I think was 8 or 9 years. Something happen that buses can get faster?

Veliladon 4y ago
As you increase the Nyquist frequency the insertion loss usually goes up stratospherically. With PCIe 3.0 we were really pushing the limits of a lot of PCB materials and link budgets were already at the edge. It required a lot of innovation to break through those limits and we also had little demand to do so. So the past decade we've basically been moving from redrivers to retimers, we've been moving up to better PCB materials with lower channel losses, we've been preparing for a PAM-4 migration in a future PCIe revision, and tons of other little changes. They all add up. Plus a lot of enterprise gear moving processing to GPUs and storage to NVMe which is putting insane amounts of data over PCIe compared to older system topologies. This means we have money willing to buy better I/O which then filters down to us mere mortals over time as volume goes up and prices come down. So we've now got a fair amount of technical headroom, a good way forward, and people with money willing to pay for it. All of which are basically conducive to rapid generational improvements in performance.
rektide 4y ago
The official press release for 6.0 states: > Almost like clockwork, PCI-SIG has doubled PCIe specification bandwidth every three years to meet the challenges of emerging applications and markets. This is not a perfect cadence. 5.0 was only 2 years. 4.0 was 7 years. But it's not a bad back of napkin figure. As for buses getting faster, it's a mix of market demand and improved technology. Market demand is that we have SSDs, network cards, graphic cards, and soon expandable memory (CXL & perhaps others) that need the throughput, where-as for a while it was kind of exotic just having a 100Gbit ethernet port (12x ports worth at 3.0 speeds) or two in a system. Similarly, getting to 4GBps capable SSDs took a while, as we learned to stack layer after layer of flash & build better controllers. The demand wasn't there. But we've really scaled up a lot lately. And yeah the tech has improved. We've gotten a lot better at building transceivers. PCIe 5.0 is 32GT/s, which is "only" 60% faster than DisplayPort 2.0 which does 20GT/s over a much lower quality much more challenging channel. For PCIe 6.0, instead of jacking up the speed, we use PAM4 to effectively send two bits at a time (32Gbaud * 2bit). PCIe 7.0 will be another speed bump (64Gbaud * 2bit), and isn't going to be super easy, but we'll have very carefully specified channels, be using newer lower-power higher-efficiency designs... it'll be hard but we need that high target to shoot for, to have growing room. In some ways, this is all just downstream of what datacenter ethernet does & needs. 400Gbe is here & often uses 8 lane connections (QSFP-DD), so 50GT/s on each lane from the switch to the transciever and/or cable (which by the way look awesome [1]). But we're already well underway doubling that, to 800Gbe and terabit ethernets, so we're already making quite a lot of silicon that does 64GT/s+. Simply leveraging what we know about signalling in other places, & bringing that wisdom & experience to PCIe, makes sense. [1] https://www.fs.com/products/82459.html?attribute=3424&id=175976 https://www.fs.com/products/82459.html?attribute=3424&id=175...

Veliladon 4y ago

As you increase the Nyquist frequency the insertion loss usually goes up stratospherically. With PCIe 3.0 we were really pushing the limits of a lot of PCB materials and link budgets were already at the edge. It required a lot of innovation to break through those limits and we also had little demand to do so. So the past decade we've basically been moving from redrivers to retimers, we've been moving up to better PCB materials with lower channel losses, we've been preparing for a PAM-4 migration in a future PCIe revision, and tons of other little changes. They all add up. Plus a lot of enterprise gear moving processing to GPUs and storage to NVMe which is putting insane amounts of data over PCIe compared to older system topologies. This means we have money willing to buy better I/O which then filters down to us mere mortals over time as volume goes up and prices come down. So we've now got a fair amount of technical headroom, a good way forward, and people with money willing to pay for it. All of which are basically conducive to rapid generational improvements in performance.

rektide 4y ago

The official press release for 6.0 states: > Almost like clockwork, PCI-SIG has doubled PCIe specification bandwidth every three years to meet the challenges of emerging applications and markets. This is not a perfect cadence. 5.0 was only 2 years. 4.0 was 7 years. But it's not a bad back of napkin figure. As for buses getting faster, it's a mix of market demand and improved technology. Market demand is that we have SSDs, network cards, graphic cards, and soon expandable memory (CXL & perhaps others) that need the throughput, where-as for a while it was kind of exotic just having a 100Gbit ethernet port (12x ports worth at 3.0 speeds) or two in a system. Similarly, getting to 4GBps capable SSDs took a while, as we learned to stack layer after layer of flash & build better controllers. The demand wasn't there. But we've really scaled up a lot lately. And yeah the tech has improved. We've gotten a lot better at building transceivers. PCIe 5.0 is 32GT/s, which is "only" 60% faster than DisplayPort 2.0 which does 20GT/s over a much lower quality much more challenging channel. For PCIe 6.0, instead of jacking up the speed, we use PAM4 to effectively send two bits at a time (32Gbaud * 2bit). PCIe 7.0 will be another speed bump (64Gbaud * 2bit), and isn't going to be super easy, but we'll have very carefully specified channels, be using newer lower-power higher-efficiency designs... it'll be hard but we need that high target to shoot for, to have growing room. In some ways, this is all just downstream of what datacenter ethernet does & needs. 400Gbe is here & often uses 8 lane connections (QSFP-DD), so 50GT/s on each lane from the switch to the transciever and/or cable (which by the way look awesome [1]). But we're already well underway doubling that, to 800Gbe and terabit ethernets, so we're already making quite a lot of silicon that does 64GT/s+. Simply leveraging what we know about signalling in other places, & bringing that wisdom & experience to PCIe, makes sense. [1] https://www.fs.com/products/82459.html?attribute=3424&id=175976 https://www.fs.com/products/82459.html?attribute=3424&id=175...