I used to work in EDA/Semi-IP as well. In addition to the common argument that tool changes are avoided to mitigate risk because of expensive iteration costs, a

I used to work in EDA/Semi-IP as well. In addition to the common argument that tool changes are avoided to mitigate risk because of expensive iteration costs, another rationale is that the design and manufacturing costs of making a chip are so high that integrators are less fixated on switching tools for savings because they are not that significant to the overall budget.