Well no, but the tools have definitely abstracted a huge ammount of design away from the Digital designer. Standard cells, along with standard register/RAM bloc

Well no, but the tools have definitely abstracted a huge ammount of design away from the Digital designer. Standard cells, along with standard register/RAM blocks, make Verilog(or VHDL in Europe) the only reasonable way to generate the complex systems manufactured in the latest processes (e.g. 5nm, but really anything that's not mixed signal). The EDA process flow starts with a design, which leads to code that with co-designed tests (as well as automated verification) that generates a netlist. That netlist is what gets "compiled" into silicon for a particular process... there's still moving blocks around and checking timing closure, temperature, and a zillion other things, but reverse engineering what individual transistors are doing in one of those blocks (much less what the block is doing) is pretty insane. Then after layout, there are automated Design Rule Checks and Layout Vs Schematic checks... which wouldn't really be possible, if you didn't have a very automated way of generating the schematic in the first place. At small geometries even the areas in between the wires and transistors has to be filled with just the right patterns so that lithography/etching works at those sizes. So certainly there are human developers, but they are (mostly) writing code that get's turned into working silicon... after a bunch of other less automated checks to make sure it won't break in less obvious ways.