RISC fell by the wayside decades ago. Two of them. It was really only ever a design touchstone, a reminder that simple operations are easier to fit into a shor

RISC fell by the wayside decades ago. Two of them. It was really only ever a design touchstone, a reminder that simple operations are easier to fit into a short clock cycle, and complex instructions are not necessarily faster than a series of simple ones. Since the time RISC still was considered a plausible thing, we got cache footprints, and micro-ops in a cache of their own. What matters, ultimately, is performance. RISC was once a means to get performance. Nowadays we do all kinds of crazy shit to get performance, very little of it compatible with what RISC was supposed to enable. So anyway maybe a mistake to put in the name.