And that's why RISC processors expose more architectural registers than CISC processors. (A read-modify-write instruction on a CISC processor will still implic

And that's why RISC processors expose more architectural registers than CISC processors. (A read-modify-write instruction on a CISC processor will still implicitly need a temporary physical register; RISC processors simply expose a larger set of logical registers since a lot of these implicit temporary registers become explicit.)