Agreed, but the point was that state machine, iterative, blocking pipeline stages are pretty common even in RISC cores, including particularly ascetic RISC-V an

Agreed, but the point was that state machine, iterative, blocking pipeline stages are pretty common even in RISC cores, including particularly ascetic RISC-V and ARM cores. But I can get how at ~12k gates you don't even want the slowest iterative divide unit.