3 ms·
> which means your decoder has to support a dozen ADDs, a dozen SUBs, a dozen XORs Does it? The way I've always internalized it is the SIB and MOD/RM are just
by akira2501 4y ago
> which means your decoder has to support a dozen ADDs, a dozen SUBs, a dozen XORs
Does it? The way I've always internalized it is the SIB and MOD/RM are just adding AGU options to the instruction. They're there in the underlying microcode set, and x86 just happens to give me direct access to them through opcode extensions. Is that not how it's actually implemented?
- NobodyNada 4y agoI have no idea how it's implemented under-the-hood, I don't even know what any of those acronyms stand for :) Regardless of how it's implemented, I don't believe it changes my point that an 'ADD mem, reg' really is at least 3 separate operations, and code density is the only potential benefit to expressing them as a single instruction (on a modern architecture). If you have suggestions as to how I should reword my comment, I'm happy to make edits.
- rep_lodsb 4y agoYes, the address unit handles the shift+add (both on x86 and ARM). That everything is translated into RISC-like "microcode" is a bit of a meme, it was only really true for the first generation 8086/8088 (from 1978). Those early chips actually had microcode subroutines to compute for example BX+DI and move the result into an internal address register. But every following x86 generation did it in hardware. Modern CPUs with out-of-order execution do break read/modify/write instructions into separate micro-ops however.