4 ms·

I think RVC is more or less universal if we're talking higher end than really simple micro-controllers or university student projects.

• snvzz 4y ago
  C is also part of RVA20 and RVA22.
• hajile 4y ago
  Even really simple MCs are likely going to use compressed instructions. RISC-V apparently takes something like 8k gates. Compressed instructions take around 400 gates or 5% more area in this case. SRAM need 6 transistors, so just 67 bits or a bit less than 8.5 bytes of storage reduction is enough to make this worth the gate cost. If you have just 1kb of I-cache, a 10% savings or 100 bytes would be 10x the cost of implementing compressed instructions. In short, I can't think of any reason you'd target a 32-bit microcontroller RISC-V design and not decide to also implement compressed instructions. If you're so sensitive to this cost, there are probably 8/16-bit MCs that would be a better choice.
  • kragen 4y ago
    Most microcontrollers don't have I-cache, and I don't know of any 8/16 bit CPU cores that are significantly smaller on an FPGA than the SeRV implementation of RISC-V, which fits in 200 4-LUTs. Do you? PicoBlaze in particular is about the same size as SeRV (96 6-LUTs I think) and really limited even compared to other 8-bit cores. It's a lot faster than SeRV, though, and has denser code—it has to, since its maximum program size is 1024 instructions. SeRV's RISC-V support lets you compile your code with GCC or clang. I do agree with your broader point that the C extension trades off a bit of decode complexity against a tiny amount of program memory size, even if that's mask ROM or something instead of SRAM I$, so there are not many cases where omitting the C extension is a good tradeoff. Just, I'm not sure the architectural data word width really bears on this.
    • hajile 4y ago
      I-cache was just one example that most people find easy to understand. The original paper on compressed instructions claims 25-30% reduction in total instruction size. A typical small M0 microcontroller will have something like 4-32kb of RAM and 32kb to 1MB of flash storage. No matter how you slice it, saving 30% of your instruction space is a HUGE deal. Even with EEPROM (usually used for flash memory) taking just 2 transistors per bit, we're still talking about compressed instructions taking up 200 bits, 40 bytes, or just TEN 32-bit instructions in your flash memory. With that 30% optimistic number, any program with more than 30 instructions will have a net benefit from compressed instructions. Even my very pessimistic 10% number would mean just 100 instructions before you break even.
  • brucehoult 4y ago
    While I agree with the principle and overall conclusion I think you're probably confusing gates and transistors. While you can make a 2-input NAND gate on a breadboard using one transistor and some resistors, in a CMOS chip resistors are more expensive than transistors (and suck energy) so actually a 2-input NAND gate will use 4 transistors, a 3-input NAND will use 6 transistors etc. You might be confusing LUTs and gates also. Regardless, by the time you have a couple of KB of ITIM or icache or maybe 10 KB of code executed directly from flash, you're better off implementing C. On anything running a real OS it's just ludicrous not to have C.
• bpye 4y ago
  RVC is designed such that all compressed instructions expand to a single full length instruction. So it’s really only the decode stage and the PC alignment that change.
• kragen 4y ago
  Even really simple microcontrollers and university student projects are probably RV32 rather than RV64.