4 ms·
Are there really (enough) RISC V cores having no microcode sequencer at all and would have to add one just to implement a 1 bit per cycle microcoded divide inst
by crest 4y ago
Are there really (enough) RISC V cores having no microcode sequencer at all and would have to add one just to implement a 1 bit per cycle microcoded divide instruction?
- bpye 4y agoI can’t think of many RISC-V cores that are microcode sequenced. There are some toy implementations using ucode - but I can’t think of any that have seen serious use. Maybe you’d count SERV?
- monocasa 4y agoIf you take a step back and define the concept in question as 'cores that have pipeline stages that can block the pipeline as they work their way through a core local state machine (whether that state machine is encoded in a table form via microcode or via a sea of logic)', then there's quite a few on the low end for multiply support. Remember that RV32EM is competing with Cortex-M0, which can get down to 12k gates when it has an iterative, bit-serial multiply.
- bpye 4y agoWhilst true for multiply, divide is considerably more complex. You have to step up to the M3 to get a divide instruction on the ARM side. This is why the new Zmmul is valuable over the existing M extension.
- monocasa 4y agoAgreed, but the point was that state machine, iterative, blocking pipeline stages are pretty common even in RISC cores, including particularly ascetic RISC-V and ARM cores. But I can get how at ~12k gates you don't even want the slowest iterative divide unit.
- deleted 4y ago[deleted]