4 ms·

that sounds like a fun project! a suite of minimal m-mode code that implements your selection of “couldn’t bother to have hardware”. want to work on it with me?

that sounds like a fun project! a suite of minimal m-mode code that implements your selection of “couldn’t bother to have hardware”. want to work on it with me? :)

brucehoult 4y ago
Just link Spike into SBI :-) I have thought that it would be good to have M-mode emulation available of everything except rv32i/rv64i. The AMO operations are a prime candidate. Very annoying for a simple implementation to have to implement read-modify-write in hardware. You can emulate AMOs easily using LR/SC, and in simple single-core systems those are no-ops anyway. It would be handy to have a special trap vector for illegal instruction, to save a few instructions checking mcause in the normal trap handler. It would also be awesome to have some special CSRs that presented the contents of the rs1, rs2, rs3 encoded in the instruction and another CSR you could write to that put the value into rd. That would save a whole lot of mucking about extracting the register specifier fields from the opcode yourself, and then having to use a switch to read or write each register (or, worse, dump all registers into RAM and then access them as an array). You might think you'd want another CSR that holds the decoded value of the literal/offset in I, S, SB, U, UJ instruction formats -- but you probably don't want to be emulating any of the basic I ISA. Maybe LB/LBU/SB/LH/LHU/SH? Those can be a pain, and are seldom used.
- crest 4y ago
  The AMO aren't NOPs in the presence of any other bus master like DMA engines found on all but the cheapest microcontrollers.
  - monocasa 4y ago
    I'm not sure that slightly more complex ucontroller archs with DMA engines require AMOs to be coherent with other masters like DMA engines. You normally do a song and dance where you just guarantee that you don't need atomic RMW in the first place, handing off filled in descriptors to the peripherals and getting interrupts on completion. But interrupts themselves complicate AMOs making them not nops and needing a CLI/RMW/STI sequence.
- bpye 4y ago
  Are LB and friends really that much of a pain? The alignment requirements mean they can all be implemented as the full XLEN version with a mask/shift.
  - brucehoult 4y ago
    Enough of a pain that SiFive cores take a whole extra cycle for LB/LH (and LW on 64 bit) from L1 cache compared to loading a full register e.g. 3 vs 2.

that sounds like a fun project! a suite of minimal m-mode code that implements your selection of “couldn’t bother to have hardware”. want to work on it with me? :)

brucehoult 4y ago

Just link Spike into SBI :-) I have thought that it would be good to have M-mode emulation available of everything except rv32i/rv64i. The AMO operations are a prime candidate. Very annoying for a simple implementation to have to implement read-modify-write in hardware. You can emulate AMOs easily using LR/SC, and in simple single-core systems those are no-ops anyway. It would be handy to have a special trap vector for illegal instruction, to save a few instructions checking mcause in the normal trap handler. It would also be awesome to have some special CSRs that presented the contents of the rs1, rs2, rs3 encoded in the instruction and another CSR you could write to that put the value into rd. That would save a whole lot of mucking about extracting the register specifier fields from the opcode yourself, and then having to use a switch to read or write each register (or, worse, dump all registers into RAM and then access them as an array). You might think you'd want another CSR that holds the decoded value of the literal/offset in I, S, SB, U, UJ instruction formats -- but you probably don't want to be emulating any of the basic I ISA. Maybe LB/LBU/SB/LH/LHU/SH? Those can be a pain, and are seldom used.

crest 4y ago
The AMO aren't NOPs in the presence of any other bus master like DMA engines found on all but the cheapest microcontrollers.
- monocasa 4y ago
  I'm not sure that slightly more complex ucontroller archs with DMA engines require AMOs to be coherent with other masters like DMA engines. You normally do a song and dance where you just guarantee that you don't need atomic RMW in the first place, handing off filled in descriptors to the peripherals and getting interrupts on completion. But interrupts themselves complicate AMOs making them not nops and needing a CLI/RMW/STI sequence.
bpye 4y ago
Are LB and friends really that much of a pain? The alignment requirements mean they can all be implemented as the full XLEN version with a mask/shift.
- brucehoult 4y ago
  Enough of a pain that SiFive cores take a whole extra cycle for LB/LH (and LW on 64 bit) from L1 cache compared to loading a full register e.g. 3 vs 2.